adc_singlerun_tb
Project Library Model Name Kind
ISCD_IADC adc_tb adc_singlerun_tb Hierarchical Module

Parameters

Name Type Default Description
ELN_sample_time double 20.0 ELN computing sample time [ns]
Comp_BW double 1.0e4 ADC comparator bandwidth
signal_source bool false Select sinusoidal (false) or ramp (true) input

Description

hierarchic symbol

Schematic

p n v_sup init_value = 3.3 offset = 3.3 gnd p n inp vin scale = 1.0 tdf_o sinusoidal_source <double> ampl = {T}{1} freq = 1000.0 offset = {T}{0} phase = 0.0 delay = sc_core::sc_time(2.0,SC_US) sampling_time = sc_core::sc_time(p.ELN_sample_time,SC_NS) SIN_SRC_TDF A t clk50m_i resn_i adc_o eoc_o vsup vin_p vin_n vref_p vref_n DUT c = 10e-12 r = 2e6 intgain = 250 compbw = p.Comp_BW IADC p n refp init_value = 1.9 offset = 1.9 amplitude = 0.0 frequency = 0.0 phase = 0.0 delay = sc_core::SC_ZERO_TIME ac_amplitude = 0.0 ac_phase = 0.0 ac_noise_amplitude = 0.0 p n refn init_value = 0.6 offset = 0.6 amplitude = 0.0 frequency = 0.0 phase = 0.0 delay = sc_core::SC_ZERO_TIME ac_amplitude = 0.0 ac_phase = 0.0 ac_noise_amplitude = 0.0 gnd clk_o i_clock_src_sc1 <bool> high_level = {T}{1} low_level = {T}{0} period = sc_core::sc_time(1.0/50.0,sc_core::SC_US) start_time = sc_core::SC_ZERO_TIME duty_cycle = 0.5 CLOCK_SRC_SC t high_level low_level sc_o i_pwc_src_sc1 <bool> init_val = {T}(0) time_vector = create_vector<double>(2e-6,2100e-6,2200e-6); value_vector = create_vector<{T}>(1,0,1) repeat = false PWC_SRC_SC<T> sc_i clk_i <int> i_file_out_clk_sc1 fname = "ADC_out.dat" fheader = "%signal" store_time = false separator = ' ' format_int = file_out_clk_sc<{T}>::DEC format_float = file_out_clk_sc<{T}>::GENERAL precision = 15 file_format = file_out_clk_sc<{T}>::ASCII FILE_OUT_CLK_SC integrating ADC testbench, run for >3ms Carinthia University of Applied Science Author: W. Scherr, Date: JAN 2021 scrollfixer scrollfixer ELN_sample_time = 20.0 Comp_BW = 1.0e4 tdf_o ramp_source wave = {0.0,-1.0, 0.1e-3,-1.0, 2.1e-3,+1.0, 3e-3,+1.0} repeat = true sampling_time = sc_core::sc_time(p.ELN_sample_time,SC_NS) t A PWL_SRC_TDF tdf0_i tdf1_i tdf_o <double> signal_selector ctrl = p.signal_source signal_source = false vsup diff_sin vin_p ref_n ref_p adc_o clk resn vin_n eoc_o diff_ramp