Create SystemC-AMS models from SPICE netlists

The idea of this procedure was presented in the "SystemC-AMS & Coside User Group Meeting" 2020.
With such an approach it will be possible to generate SystemC-AMS models by any schematic entry which generates SPICE netlists.
This should allow designers, familar with SPICE macro modelling, to have an easy transition to faster and more versatile SystemC-AMS concept models. These analogue models can be then used by system engineers for existing IP to be re-used, in a similar fashion as SystemC code can be already created e.g. from (digital) Verilog or VHDL code.
I am also thinking about supporting Spectre netlists, so users of the CDS could use Virtuoso and Analoglib to create SystemC-AMS models "out of the box" as well.

Proof of Concept

I have some initial framework which allows me to create correct SystemC-AMS code of very simple netlists already:
/pics/spice_nl.png /pics/arrow.png /pics/scams_h.png /pics/scams_cpp.png
Currently I am experimenting with SPICE netlists created by XCircuit.

Project status:

  • Development setup: Python using Spyder
    (initial idea: C++; I started to use a compiler-compiler from JKU Linz, which would have been a more "formal correct" method - I had some smaller issues, unfortunately I never got any response from the maintainer of the tool, so I had to assume it was no longer in use - so I better didn't start with it)

  • Status in form of a "mini Kanban list" instead of a table:
    • spice file reader, multiline handler, tokenizer: ok
    • base classes to handle netlists, nodes, terminals, primitives: ok
    • write cpp and h files using templates: ok
    • subcircuit handler: ok

    • primitive elements implemented: R, L, C, E (ongoing)
    • parameters on primitives and subcircuits: ongoing

    • subcircuit instances (X): open
    • nonlinear instances (M,B,...): open
    • special (A/Z) primitive elements (logic, ...): open
More to follow soon!