|(c) 2021 Carinthia University of Applied Sciences. All rights reserved.
This model is for educational purposes only. Use at your own risk.
It was developed using Coside v2.7.1, from COSEDA Technologies GmbH.
For more information, contact the author: firstname.lastname@example.org.
This model illustrates the design implemented in the ISCD study program throughout three semester. It comprises an integrating, dual slope analog to digital converter (IADC) running at 50MHz. It will be designed in a 130nm technology, produced by the Europractice program and finally assembled and verified in the lab.
This model will be set up by the students in a three hour session (roughly) for the "System Modeling and Verification - Analog" (SYSMOD-ANA) class. It contains some basic blocks using ELN and DE modeling. It also shows some basic features of Coside. This release version is just cleaned-up a bit. The lectures also cover HDL languages like VHDL-AMS and Verilog-AMS and implementing RNM models in standard digital simulators using VHDL, SystemVerilog and SystemC (but this is not part of this particular model, of course).
Please note: this model is not fully optimised, it is just a starting point for further analysis and studies and shows some basic aspects of model parameters and simulation setup.
Stand alone test benches (run with SCSimControl out of the schematics):
The simulations (including the IADC testbench) will only require a few seconds to run (depending on your compute HW).
Run with Octave (or Matlab):
Please note: do not edit the .m scripts in the DEBUG folder, they will be overwritten by the versions found in the '<workspace-path>/ISCD_IADC/automation' project folder. Thus, edit files there and use 'build all' to copy them over there, before you run them again.
Click on the image above to navigate through the model documentation, starting from the IADC testbench.
Full project documentation (auto-generated)
Please start with this link here.
The Octave script shows the different results while varying a sub block parameter (bandwidth of the comparator) and the ELN sample time.
First two figures show the samples over time and frequency using the sinusoidal source, the last two figures shows the transient result and a histogram using the ramp source.
It shall demonstrate the different aspects of modeling and their effects on results and how to tackle them correctly, without slowing down simulations for the wrong reasons. Finally the problem lies in the model itself and shows that e.g. the comparator could be improved by an analog reset to be faster to find the decision.