logic_test
Project Library Model Name Kind
eln_examples eln_logic logic_test Hierarchical Module

Description

test bench for all ELN logic elements

Long Description

TESTBENCH for ELN based logic elements

This gates allows keeping circuits completely in the ELN cluster, but use with care.

It may be more efficient in case of more logic required to use TDF logic instead.

Schematic

ELN based logic gates, educational use only. (c) Carinthia University of Applied Sciences zoom bugfix vout pulse_a vdd = 1.0 delay_time = 0.0 low_time = 0.5e-6 high_time = 0.5e-6 sampling_time = sc_core::sc_time(0.01,SC_US) dly low high vout pulse_b vdd = 1.0 delay_time = 0.25e-6 low_time = 0.5e-6 high_time = 0.5e-6 sampling_time = sc_core::sc_time(0.01,SC_US) dly low high A Y i_eln_inv1 vdd = 1.0 delay = 1e-12 A B Y i_eln_and21 vdd = 1.0 A B Y i_eln_nand21 vdd = 1.0 A B Y i_eln_or21 vdd = 1.0 A B Y i_eln_nor21 vdd = 1.0 A B Y i_eln_xor21 vdd = 1.0 A B Y i_eln_xnor21 vdd = 1.0 res set q qn i_eln_rslatch1 R S Q Qn zoom bugfix a b vinv vand vnand vor vnor vxor vxnor vrs vrs_n